The present invention relates to a code-amount control device and more particularly to a code-amount control device for controlling the amount of codes to be generated for encoding each block of video data in such a way that the code length of the coded block shall not exceed a specified target value when the code-amount control device is used in a video coding device for high efficiency encoding a video signal by interframe prediction method, and to the video coding device including the code-amount control device.
To record and transmit video information containing a very large amount of data, it is usually needed to reduce a rate of coded data by so called &lt;image compression&gt; or &lt;high efficiency encoding&gt; technique to a level at which the data can be recorded or transmitted without visually noticeable degradation of image quality or the data can have enough time to be recorded.
The MPEG method is a representative example of the high-efficiency coding technique. The MPEG method is established as standards ISO/IEC11172 and 13818, wherein interframe coding and variable-length coding are combined to realize a high efficiency video coding.
The MPEG coding device comprises a image memory, a motion-vector detecting circuit, a subtracter, a DCT (Discrete Cosine Transform) circuit, a quantization circuit, a variable-length coding circuit, an output buffer, an inverse quantization circuit, an inverse DCT circuit, an adder circuit, a decoded image memory, a predicted image generating circuit and a rate control circuit.
The operation of the coding device is as follows:
The image memory stores, for example, an input digital image signal in the format of 4:2:0 (cf. ITU-R Recommendation 601) and outputs the signal in macro blocks. A luminance signal is composed of macro blocks each consisting of 16.times.16 pixels while a chrominance signal is composed of macro block each consisting of 8.times.8 pixels. The processing operation is performed on every macro block. The motion vector detecting circuit receives from the image memory macroblock data of an image to be encoded and reference image data used for searching motion vectors and detects the motion vectors. The detected motion vectors are input to the decoded image memory that in turn outputs pixel data necessary for generating a predictive image to the predicted image generating circuit by which a predicted image is then generated. The subtracter subtracts the predicted image from the original image and outputs the subtraction result to the DCT circuit that in turn performs the discrete cosine transform of differential image data for each of blocks (8.times.8 pixels) of and outputs DCT coefficients. The quantization circuit selects a matrix for quantizing and quantizes the DCT coefficients according to a signal from the rate control circuit (to be described later) and outputs quantized values. The matrix for quantization is a set of quantization step sizes corresponding to DCT coefficients of 8.times.8 pixels. The variable-length coding circuit encodes with variable code length a set of continuous zeros (hereinafter referred to as zero run) followed by non-zero quantized values (hereinafter referred to as levels). The variable-length coded data is temporally stored in the output buffer and then output therefrom.
The quantized values outputted from the quantization circuit are also input to the inverse quantization circuit by which the values are inversely quantized. The inversely quantized values are then subjected to inverse discrete-cosine transform and added to the predicted image outputted from the predicted image generating circuit to produce decode data that will be stored in the decoded image memory. The decoded image data is used as predicted image data.
The amount of generated codes can be controlled by the rate control circuit that, observing occupied ratio of the output buffer, determines the number of bits to be allocated to macro blocks and controls the quantization matrix in such a way that the coded data may does not exceed the allocated number of bits. The quantization matrix is controlled to increase or decrease its value for reducing or increasing the amount of producible codes as the vacancy of the output buffer decreased or increased.
The above-mentioned system with the rate control circuit for controlling the value of the quantization matrix according to the vacancy of the output buffer uses a variable length coding method and, therefore, can not assure that the amount of generated codes becomes equal to the allocated number of bits. In addition, the MPEG method uses allocation of maximum 28 bits for an input image data whose pixel is represented by 8 bits, so MPEG method may generate very large amount of codes in comparison with amount of original image data in a short period.
Namely, such coded data that may have different amounts of generated codes must be processed by a processor whose capacity is enough to process a maximal bit rate of the coded data. This makes the hardware be very large.
Japanese Laid-open Patent Publication (TOKKAI HEI) No. 4-307887 discloses a rate control method that may reduce variation of the amount of codes to be generated. This method counts the amount of codes generated by variable-length encoding step and, if either of an average amount and a peak amount of generated codes exceeds a preset value, encodes a specified number of macro blocks and, after this, rounds off all the coefficients considered as zero.
There shows an example of application of the rate control method disclosed in Japanese Laid-open Patent Publication (TOKKAI HEI) No. 4-307887, which is applied to the video coding device above-mentioned. The video coding device differs from the above-mentioned MPEG coding device by the operation of its variable-length coding circuit and rate control circuit. Namely, the rate control circuit sets a target code-amount for each macro block and counts every code outputted from the variable-length coding circuit. The rate control circuit outputs a control signal to stop the operation of the variable-length coding circuit when the counted amount of codes exceeds the target value. By doing so, the amount of generated codes can be kept less than the target value.
However, the coding device after-mentioned requires the variable-length decoding circuit in addition to the coding device above-mentioned. Namely, the remaining coefficients are rounded off by the variable-length coding circuit and, therefore, an image decoded directly from the output of the quantization circuit and stored in the decoded image memory may differ from an image decoded by the decoding side. The variable-length decoding circuit must be provided with a table for restoring the variable-length code composed of the zero run and level values, which may have a large scale circuitry.